Control mechanism and bus for a data processing pooler system

ABSTRACT

An improved data processing pooler system for pooling data cooperatively to a central computer compatible magnetic tape or tapes from other computer compatible magnetic tape or tapes, utilizing key-to-tape units, each key-to-tape unit having devicecontrol-area (DCA) units as an interface between said key-to-tape units, said DCA&#39;&#39;s being coupled to each other by a pooler bus of the &#39;&#39;&#39;&#39;hand shake&#39;&#39;&#39;&#39; type having a plurality of bidirectional lines for transmitting or receiving control and/or data signals. The system comprises input/output devices of the key-to-tape type, one device having a master pooler adapter and controls capable of operating as the master or control pooler unit, whereas the other devices have a slave pooler and controls capable of operating as slave or controlled pooler unit(s). An input/output (I/O) bus connects a central processor (CCU or CPU) unit in each key-totape unit with the device-control-area (DCA) also in each key-totape unit; said I/O bus contains a group of bi-directional multifunction lines, single function lines and a second group of control lines which form an array. Sending key-to-tape units and receiving key-to-tape units, each individually having its own memory, are connected by a pooler bus, and interfaced via the key-to-tape device-control areas (DCA&#39;&#39;s) which contain the necessary logic to link the sending and receiving pooler adapters together, and to provide the control of information flow to and/or from the respective sending and receiving memories. Additional logic circuitry write and/or read information into or out of said memories and onto or out of the magnetic tapes.

United States Patent [:91 n Yu 45 Feb. 6, 1973 [s41 cosrnor. MECHANISM AND BUS FOR ABSTRACT A DATA PRQCESSING POOLER An improved data processing pooler system for pool- S S ing data cooperatively to a central computer compati- 75 Inventor: Frank K. Yu, Burlington, Mass. s"=" p of tapes from h r p p patlble magnetic tape or tapes, utilizing key-to-tape Asslgrleei "mmywell, Mlnneapolls. Mlnnunits, each key-to-tape unit having device-control-area 1 l 970 (D CA) units as an interface between said key-to-tape [22] Flled June 1 units, said DCAs being coupled to each other by a [2i Appl. No.: 45,523 pooler bus of the "hand shake" type having a plurality of bidirectional lines for transmitting or receiving control and/or data signals. The system comprises in- [52] US. Cl. put/output devices of the key to tape type one device n I having a master pooler adapter and c t ols capab e [58] Field of Search ..340/l72.5 of operating as the master or control pooler unit, whereas the other devices have a slave pooler and References Cited controls capable of operating as slave or controlled pooler unit(s). An input/output (l/O) bus connects a UNITED STATES PATENTS central processor (CCU or CPU) unit in each key-to- 3,480,914 ll/l969 Schlaeppi ..340/l72.5 tape unit with the device-control-area (DCA) also in 3,274,554 9/1966 Hopper et al ..340/l72.5 each key-to-tape unit; said l/O bus contains a group of 3,372,378 3/1968 Devore et al ..340/l72.5 bi-directional multifunction lines, single function lines 3.400.373 9/1963 Nicholson A ..340/l72.5 and a second group of control lines which form an ar- 3,4l6,|39 |2/l963 a ..340/172.5 ray. Sending key-to-tape units and receiving key-to Dl'lSCOll tape units each having its own memory 3,470,542 9/1959 Tramanena X are connected by a pooler bus, and interfaced via the 3,482,215 l2/l969 Murayama ..340/l72.5 key to tape device comro| areas (DCAvs) which 3'530'440 9/1970 OSPOmC 1 3 tain the necessary logic to link the sending and receivi i i ing pooler adapters together, and to provide the con- 3623'002 $1971 z'z i "340/172'5 trol of information flow to and/or from the respective y sending and receiving memories. Additional logic cir- 3,623,0ll ll/l97l Baynard,.lr. et al. ..340Il72.5

cultry wr teandlor read information into or out of said Primary Exa miner Paull. ll e npn 7W "Whn memories 58. or 5 "$2: tapes Assistant Examiner- Melvin B. Chapieck g Atmmey- Fred Jacob and Leo Stanger 44 MIN GDNTlUl. 4 CENTRAL 4 NUXlLINllY CUNTROL (L STATION UNIT CONTROL UNIT STNTIOI UNIT 42 1 N68 CONTRUL IAIN l MIXlLIARY l/ 1 PAIIEL AREA l HEUORT AREA comm mm 1 I "w" M 12 ,4! NDAPTEHPDDLER) i I "m" GEIITROL met AAEA I CONTROL l I l GOIITRULLER Am mm column 1 ."Yimet AREA i AREA 0m A L m z ADAPTERS) J l 1 ms "0 rnArrlc L ----K *J I INTEITFNCE{ TAPE UNIT 40 AREA r TAPE ranas r m r AmoAno l l NIH 2D 24 l as 1 TAPE 22 A |1E A 1 35 l ADAPTER AREA 1 A n g ggggg H ARM T0 UTNEll PWLER 30 L J DEVICE comm i AREA UNIT PATENTEDFEB 6I975 3,715,727

SHEET [11 [1F 20 44 RAIN CONTROL 46 0mm 10 AUXILIARY CONTROL STATION UNIT CONTROL UNIT STATION UNIT r 42 N05 CONTROL MAIN 1 I AUXILIARY 7f PANEE AREA l MEHORYAREA I CONTROL PANEL I 43 I 5a 42 I I 12 14 I ADAPTER (POOLER) I I I A EMORY I I CENTROL PANEL AREA I I CONTROL I coNTRoLEER AREA I I 'ADTPT'E'R WNW)? I I 16 18 I PANEL AREA 1 I L (IF 2 ADAPTERS) J I HOITRAFFIC I i I INTEREAcE I TAPE UNIT AREA I -i fi I I TAPE I 20 I- TRANsPoRT I AREA I, KEYBOARD i I AREA 20 I 24 7 A as TAPE 22 I A E i 26 ADAPTER AREA- I ATTACHMENT (IF 2 AoAPTERs) 32 (IF 2 ADAPTERS) ADAPTER POOLER 7 TO OTHER POOLER I I I DEVICE CONTROL 49 AREA UNIT Fig. I.

L'YYIZYIOR FRANK K. YU

PAIENTEDFEB 6 1975 3.715.727

SHEER 03 HF 20 SET-UP roa mam mu musmmn mu DEPRESS RUN I D 5i! 0" RECORD ""0 MASTER PURE (BUFFER)! K a ADDRESS URI E*PO0LER PDDLER RECEW (DC (DDAJX moamm (IPS),(BIS);

GATE DATA OR PODLER BUS (ISB) GENERATE INFO REDDRD LENGTH IR gnnon HDLD DATA OR BUS HALT PODLUE DPERATIDR INVENTOR FRANK K. YU F W PATENIEUFEB BISH 3.715.727

SHEEI OSUF 20 xm m POOLER BUS gag

RU 511? sun m0 ncv m POOLER m BUS PRV Fig. 5B.

PATENTEDFEB ems 3.715721 SHEET UBUF 20 RESET sum RUN APRSTIA RESET SUP'SUX sn UP POOLER APSTR sum n.c.ouasrzo mm] TOTSI TRAFFIC STATE'ONE' mun RESET aunou DEPRESSED mm mo smsnecnus TPTRC TAPE mm. mnsunm DCA AND m W54 om VERIFY MODE mun STARTBUTTONDEPRESSED RUN BUTTON FIRST RECORD READ m mo MEMORY m RUN BUTTON nmesssn rmsr coumu mo AND 9'- xmmo T0 RECEIVER DOA.

RESET smn RUN APRSTIA RESET SUP'SUR SETUPRECEIVER APSTR START aunon APSTT FL RESET aunoumzmsssn unnwmrsswsnscnns M52 TRAFF'CSTATE RECEIVER non AND 1 mm) M ENTRY "ODE JINPUT um 0mm RUN nun BUTTON sum mmon DEPRESSED m MEMORY SET UP FOR FIRST COLUMN RYI "HE RUN aunon DEPRESSED um \mnuc ron KPIF'S men xumsa DCA.

Fig: 6B.

PATENTED FEB APXH KPRCV APTIID APIIANIZ APRUNSA APFIOD AP TSTIZ APSRRID APSXRID 44o KPSRSIZ SR5 swz xPswzlz PBswFoo APSUSIZ mono SLAVE 2 SLAVE 3 SLAVE 3 SLAVE 3 SLAVE 3 SLAVE 3 SLAVE 3 SLAVE3 SLAVE 5 Emmi;

SHEET 080E 20 APXMT 403 sum mum KPTIID KPHANIZ KPRUNSA KPFIOD KPTSTIZ APSRRID KPSXR ID SLAVE3 458 SLAVE3 SLAVE3 SLAVE 5 KPSRZIZ PBSRFOO 439 KPSRSIZ (J) APSIZIZ KPSISIZ '(L) KPDOIIO KPDOSIO D mono KPDOSIO APDOSID iii? KPDOTIO some APDOSIO KPSTPIO KPISBIO SLAVE 2 sum mmozlo m suwss ltlfifimoslo (o) suvc a llyogmmm (P) SLAVE a m KPDOSIO (m SLAVE s mtmosm (R) SLAVE s goimom (5) sum m t-KPDJUIO m u 5 m x uosro w) memo SLAVE KPSTPIO Fig:

SLAVE a m msam PATENTEDFEB 61975 3,715,727

SHEET lOUF 20 STROBELIHES ruucnou 000 000 IPG 400 000 I60 LINE 015 ms OPS-0C5 ops-00s IPS-ICS IFS-I65 oFs-ocs lPS-ICS F01 DATA A01 F01 F440 PRO ERR 40s F02 A0ATA A02 P02 TRB IDP um TEF F05 DATA A03 P83 EOD ALP MDC "Um F04 0m A04 P04 FAA BUR 0UP uncnou F05 DATA P65 VER SKP LINES F06 0m PRH AGN LZK F07 0m TEIH ISP m F08 0m TER2 ILZ REW F09 0404 THF ERO RLA ADV t ADDRESS vAun (0cA ccu) m4 INITIALIZE (ccu DOA) FDA comma mm: (000 DOA) 04F DEVICE TRANSNIT (om- 000) 01R DEVICE RECEIVE (00A ccu) MES 0m DEVICE mmAuzE (00A cc0) TSH TRAFFIC sms MODIFY (DOA- 060) usc HIGH SPEED cmmumcAFoR (DOA ccu) 0040 000 m WRITE 4400a 4000 DCA) 040 000 m VERIFY (ecu-+004) Fig 8.

PATENTEDFEH ems 3.715.727

sum 130F 2o START-UP AND TRAFFIC STATE VALIDATION poallllllllllllllllllllllllllll APSTR1A| APSTRIO APSTT1O APSTA1O APSTUIO 1 a]: im:

0cAs2T r DCASBT r DCASOT DCA 00010 DCAUND10 ocn ADV DCA ms I oca PRO 1-- TCSAT1O l TCSOT10 1 TCSIT1O r1 DCA ADDIO m TCCSHIO TCPOC IIIIIIIIIIIIIIl llllllllHl' i PATENIEDFEEI W 3,715,727

sum 150F 20 OUTPUT INFORMATION STROBE (B15) TCOISOO FROM MEMORY CONTROLLER Fig. 115.

CONTROL STROBES HOLD TCCSH1O Fig. 116.

OUTPUT PROGRAM STROBE OUTPUT CONTROL STROBE FROM TCOPSOO FROM POA TCOCSOO MEMORY MEMORY CONTROLLER Tcopsw CONTROLLER T606510 TCCSHIO F ccs 1o Fig. 11.0. Fig. 11 E.

PATENTEDFEB 8 I975 SHEET 16 0F Zmw mm:

m6 4 m3 995 y: m 202m PAIENTEUFEB 6:975 3.715.727

sum 17UF 20 UNIT DEFINED (DRIVES ADV) SGA CSH GEN.

cumo

t CUD1O INT2O 56A csmo SGA Fig? 1 2 E.

PATENTED FEB 6 I575 $715,727

SHEET 180F 2O BIS GEN.

mew: o sm SGA B|s1o o|s1o 52W) t: osno o|s1oE SSA 01510 T IPR PRS10: SGA

Fig 126 INPUT CONTROL STROBE :c'sm

- ssno ERROR OR SPECIAL COMMANDS Fig. 12H.

PATENTEU FEB 51973 SHEET ISUF 20 Q SHN ga g F QM; F F EDSQ a A a E A A 5 c d d c A E x 9E F53 r2645 0% Q 3% x 36 E 0% #8456 52 e608? 0608: FL Z QSESU 20 3% c d d 5:83

:mE m8 02:2; 00 FDnCbO 

1. A data processing system comprising: a. first and second central processor units (CPU''s), each of said first and second CPU''s having a buffer memory respectively; b. first and second peripheral control units (PCU''s); c. first and second input/output (I/O) buses coupling said first CPU to said first PCU, and said second CPU to said second PCU, respectively; d. a peripheral bus coupling said first and second PCU''s; e. first means coupled to said first and second I/O buses and to said pooler bus for asynchronously transmitting or receiving request and acknowledge signals between said PCU''s under control of said PCU''s; f. and second means coupled to said first and second I/O buses and to said pooler bus, said second means for asynchronously and bidirectionally transmitting or receiving parallel control and data signals simultaneously between said buffer memories in each of said CPU''s over said peripheral and first and second I/O buses, under control of said PCU''s.
 1. A data processing system comprising: a. first and second central processor units (CPU''s), each of said first and second CPU''s having a buffer memory respectively; b. first and second peripheral control units (PCU''s); c. first and second input/output (I/O) buses coupling said first CPU to said first PCU, and said second CPU to said second PCU, respectively; d. a peripheral bus coupling said first and second PCU''s; e. first means coupled to said first and second I/O buses and to said pooler bus for asynchronously transmitting or receiving request and acknowledge signals between said PCU''s under control of said PCU''s; f. and second means coupled to said first and second I/O buses and to said pooler bus, said second means for asynchronously and bidirectionally transmitting or receiving parallel control and data signals simultaneously between said buffer memories in each of said CPU''s over said peripheral and first and second I/O buses, under control of said PCU''s.
 2. A data processing system as recited in claim 1 including third and fourth means for asynchronously and bidirectionally transmitting control and data signals from said first CPU to said second PCU or from said second CPU to said second PCU over said first or second I/O bus, respectively, under control of signals from said first and second I/O buses.
 3. A data processing system comprising: a. a plurality of central control units (CPU''s), each of said CPU''s having a buffer memory; b. a plurality of input/output buses coupled one each to one each of said central control units; c. a plurality of peripheral control units (PCU''s) coupled one each to one each of said input/output buses; d. a pooler bus coupled to said peripheral control units (PCU''s) for carrying information or control signals therebetween; e. first logic means coupled to said input/output buses and to said pooler bus for providing control signals for asynchronous transmission or reception of information or control signals between said buffer memories of said CPU''s, said information and/or control signals carried by said input/output and pooler buses; and f. second logic means coupled to said input/output buses and to said pooler bus for providing communication signals for asynchronously requesting and acknowledging information between said PCU''s, said second logic means under control of said PCU''s.
 4. A data processing system as recited in claim 3 including first selection means for enabling at least one of said peripheral control units (PCU''s) for transmission of information and control signals between said PCU''s and second selection means for enabling at least a second of said peripheral control units (PCU''s) for reception of information and control signals between said PCU''s.
 5. A data processing system as recited in claim 4 wherein said peripheral devices are key-to-tape units wherein one peripheral device comprises a master key-to-tape unit and the other peripheral devices comprise slave key-to-tape units.
 6. A data processing system as recited in claim 3 wherein said logic means include synchronous timing means for providing synchronous timing signals.
 7. A data processing system as recited in claim 6 wherein said logic means further include asynchronous timing means for providing asynchronous timing signals, said asynchronous signals asynchronously timing the processing of the information carried by said I/O and pooler buses, and the synchronous timing signals synchronously clocking said asynchronous signals.
 8. A data processing system as recited in claim 7 wherein said logic means further include holding means for holding the information signals carried on said pooler bus on said pooler bus until released by release means responsive to said synchronous timing signals.
 9. A data processing system comprising: a. at least one transmitter central control unit and at least one receiver central control unit; b. at least one transmitter input device, and at least one receiver output device; c. a transmitter input/output bus and a receiver input/output bus each bus having its own plurality of parallel multifunction bidirectional and single function bidirectional lines; d. first logic means in said transmitter central control unit for generating a plurality of traffic states, said first logic means coupling said transmitter input/output bus to said transmitter control unit; e. a second logic means in said receiver central control unit for generating a plurality of traffic states, said second logic mEans coupling said receiver input/output bus to said receiver central control unit; f. third logic means coupling said transmitter input device to said transmitter input/output bus, said third logic means being responsive to one or more of the traffic states generated by said first logic means; g. fourth logic means coupling said receiver input/output bus, said fourth logic means being responsive to one or more of the traffic states generated by said second logic means; and h. a pooler bus having its own plurality of parallel bidirectional lines, said pooler bus coupled to said third and fourth logic means, and said pooler bus being responsive to said third and fourth logic means for transmitting substantially simultaneously and in parallel, data signals from said transmitter input/output bus to said receiver input/output bus.
 10. A data processing system as recited in claim 9 wherein said plurality of lines of said pooler bus comprise at least two groups of lines, said groups being data lines and control lines.
 11. A data processing system as recited in claim 10 wherein said plurality of lines of each of said receiver and transmitter input/output buses comprises two groups of lines, said two groups of lines of said receiver and transmitter input/output buses being parallel bidirectional single function control lines and parallel bidirectional multi-function data lines.
 12. A data processing system as recited in claim 9 wherein said traffic states generated by said first and second logic means are four in number, traffic states 1, 2, 3 and 4, and wherein traffic states 1 and 2 are essentially input states, and traffic states 3 and 4 are essentially output states.
 13. A data processing system as recited in claim 12 including a first and second record size memory unit in said transmitter and receiver central control units, respectively, wherein data is entered into said first memory unit during traffic state 1 of said transmitter and transmitted to said second memory unit during traffic state 4 of said transmitter and traffic state 2 of said receiver and wherein data is released from said second memory unit for recording during traffic state 4 of said receiver.
 14. A data processing system as recited in claim 13 wherein said transmitter central control units and said transmitter input device and said receiver central control units and said receiver output device comprise in combination transmitter and receiver key-to-tape devices, respectively, each of said key-to-tape devices having mounted thereon computer compatible magnetic tape, and each of said transmitter key-to-tape devices including means for reading data from the magnetic tape mounted thereon into said first record size memory unit, and each receiver key-to-tape device including means for writing data from said second record size memory onto the magnetic tape mounted on said receiver key-to-tape device.
 15. A data processing system as recited in claim 9 including first selection means for enabling selected ones of said transmitter central control units for parallel transmission of information or control signals carried by said transmitter input-output bus, and second selection means for enabling selected ones of said receiver central control units for parallel reception of information or control signals carried by said receiver input/output bus.
 16. An input/output control system comprising: a. I/O bus means having a plurality of parallel multi-function and single function bidirectional lines for the parallel transmission or reception of data signals on selected ones of said parallel bidirectional multi-function lines of said I/O bus means under control of signals on said parallel bidirectional signal function lines of said I/O bus means; b. pooler bus means having a plurality of parallel bidirectional lines for the parallel transmission or reception of data on selected ones of said parallel bidirectIonal lines of said pooler bus means under control of signals on said single function bidirectional lines of said I/O bus means; c. a traffic controller coupled to said I/O bus means and pooler bus means for sequentially establishing a plurality of traffic states; d. first means responsive to said traffic states for establishing signals for controlling the parallel flow of information in response to said traffic states said first means coupled to said I/O and pooler bus means; e. second means coupled to said I/O and pooler bus means for placing information and control signals on said I/O and pooler bus means; f. and third means coupled to said I/O and pooler bus means for removing information and control signals from said I/O and pooler buses.
 17. An input/output control device as recited in claim 16 wherein said I/O bus means comprises an array of control and signal lines in columns and rows, respectively, and said pooler bus means comprises d bidirectional data lines and c bidirectional control lines where d is the number of bidirectional data lines and c is the number of bidirectional control lines.
 18. An input/output control device as recited in claim 17 wherein d is equal to 9 and c is equal to
 16. 19. In combination with a data processing pooling system comprising a master central control unit (CCU) and a slave central control unit, a plurality of input-output buses coupled to said master and slave control units, a master device control area (DCA) and a slave device control area (DCA) coupled to said input-output buses, and a pooler bus coupled to said master and slave DCA''s: a. unit-defined-logic means and said master and slave (DCA''s) for generating address valid signals in response to signals from said master and slave central control units, said address valid signals for notifying the master (CCU) that the slave (CCU) is initialized to receive information from the master (CCU); and, b. A master and slave (DCA) timing logic means for generating sequential DCA timing pulses for sequentially initiating the generation of control signals.
 20. The combination as recited in claim 19 wherein the number of sequential timing pulses generated in each DCA timing logic means is four.
 21. The combination as recited in claim 20 including means responsive to the sequential DCA timing pulses for generating request and acknowledge signals from said master and slave DCA''s to said master and slave central control units CCU''s, and for generating signals for resetting said unit-defined-logic means.
 22. In a data processing pooler system comprising at least a master and a slave central control unit (CCU) each having a traffic controller and record memory, a master and slave device control area (DCA), a master I/O bus coupling said master CCU and master DCA, and a slave I/O bus coupling said slave CCU and slave DCA, and a pooler bus coupling said master and slave DCA''s: a. first means coupled to said master record memory, said first means for reading information out of said master record memory and a first auxiliary means coupled to said master record memory and said master I/O bus, said first auxiliary means for placing the information on said master I/O bus; b. second means coupled to said master I/O bus and to said master DCA, said second means for gating the information from said master I/O bus to said master DCA; c. third means coupled to said master DCA and to said pooler bus, said third means for gating the information from said master DCA to said pooler bus; d. fourth means coupled to said pooler bus and to said slave DCA, said fourth means for gating the information from said pooler bus to said slave DCA; e. fifth means coupled to said slave DCA and to said slave I/O bus, said fifth means for placing the information from said slave DCA on said slave I/O bus; f. and sixth means coupled to said slave I/O bus and to said slave record memory, said sixth means for writing the information from said slave I/O bus into said slave record memory.
 23. The data processing pooler system as recited in claim 22 wherein said second, third and fourth means comprise AND gates.
 24. A data processing pooler system comprising a plurality of key-to-tape devices each having a central control unit (CCU); a plurality of I/O buses coupled one each to one each of said CCU''s; a pooler bus coupled to each CCU; device selection means coupled to said CCU''s, said device selection means for designating a master key-to-tape-unit, said master key-to-tape unit for transmitting information to the other of said plurality of key-to-tape devices, said device selection means including device enabling means for enabling a select-read-function. 